The present invention relates generally to semiconductor device manufacturing and, more particularly, to an LCR (inductor, capacitor, and resistor) test circuit structure for detecting metal gate defect conditions found in integrated circuits using metal gate transistors.
Semiconductor structures are now employing high-k metal gate stacks because they provide better performance at lower power and may avoid leakage resulting from device scaling. Hafnium-containing dielectrics are being used as gate dielectrics with the gate dielectric covered by a conductive layer such as titanium nitride (TiN) to protect it during high temperature deposition process of silicon (Si). The conductive layer is then covered by other semiconductor materials, such as a polysilicon layer or an amorphous silicon layer, and may be capped by a silicide cap layer. The gate stack is surrounded by a spacer material. Thus, the conductive layer is typically sealed by the spacer material of the structure. Aggressive cleaning processes are typically used after the spacer formation process.
One drawback associated with such a high-k metal gate (HKMG) fabrication process is that if a seal is violated and a path exists to the conductive layer, the conductive layer may be removed during the manufacturing process. If such an event occurs, the semiconductor device may not work properly. The detection of a gap in the conductive layer may be challenging using conventional optical or laser-based, voltage contrast (VC), or probe-able inspection techniques, because the conductive layer may be covered by other semiconductor material layers. On the other hand, existing test structures incorporated into the manufacturing process tend to have relatively small sensitivity, and may not effectively discriminate between missing metal and missing silicon.